Processing of silicon wafers is commonplace in the manufacture of modem microelectronics devices. Such processing, including plasma processing and ion implantation may be performed at low pressures, wherein RF or microwave plasmas, or high-power particle beams are delivered to the wafer, therein producing high temperatures at the wafer during processing. Such high temperatures (e.g., temperatures exceeding 100 C for conventional implants, and up to 400 C for other processes), however, can have deleterious effects on the wafer.
For many processes, precise temperature control is not required, as long as the wafer temperature remains at less than a predetermined limit, such as below 100 C in ion implantation, or less than 400 C in general. Current trends in ion implantation, however, are tending toward high power serial implanters which generally require cooling with heat transfer coefficients HTC>200 mW/cm2C and temperature control within ±5%.
In advanced implant and wafer processing operations, a precise temperature control is typically required, wherein HTC uniformity across a 300 mm wafer, for example, needs to be maintained within 1%. Such processes can have an HTC value, for example, as high as 500 mW/cm2C. It is in meeting these high performance requirements that the current invention is directed.
Wafer temperature control in semiconductor processing has utilized electrostatic chucks (ESCs) for some time. A typical single-polar ESC is illustrated in FIG. 1, wherein the ESC 10 holds the wafer 20 in place by electrostatic force. The wafer 20 is separated from an electrode 30 by an insulating layer 40. A voltage (e.g., illustrated as a +) is applied to the electrode 30 by a voltage source 50. The voltage applied to the electrode produces an electrostatic field (e.g., illustrated as a “−”) at the wafer 20 which induces an equal and opposite charge (e.g., illustrated as a +) on the wafer 20. The electrostatic field on the wafer 20 produces an electrostatic force between the wafer and the ESC 10. Consequently, the electrostatic force holds the wafer 20 against the insulating layer 40.
Cooling of the wafer 20 when utilizing ESCs can be provided by contact conductivity between the wafer and the contact surface 60 of the insulating layer 40, wherein the insulating layer may be cooled by cooling water. Conventionally, the cooling of the wafer 20 generally increases with the voltage applied to the ESC. Significantly high voltages, however, can have deleterious effects on the wafer (e.g., a cause of particle generation), and may further have costly power supply and consumption considerations, along with increased failure rates.
In vacuum environments, conventional ESCs utilize a cooling gas between the wafer 20 and the insulating layer 40, wherein a contact surface 60 of the insulating layer 40 comprises a plurality of protuberances (not shown) machined into the insulating layer, therein providing a region for the cooling gas to reside. Typically, a ceramic layer is conventionally machined to form protuberances therein, wherein the protuberances are formed by bead blasting. However, conventionally machining an insulating layer 40 comprised of a ceramic typically has several drawbacks, both in terms of precision, as well as potential particulate concerns caused by the ceramic layer during wafer processing.
Furthermore, it is typically very difficult to obtain a chuck surface flatness (i.e., control a waviness of the surface) of less than 5 microns across a 300 mm workpiece using conventional mechanical machining methods. For example, when the wafer contacts the conventional chuck surface (e.g., a ceramic chuck surface), the wafer 20 does not contact the chuck surface 60 at every location about the chuck surface, leaving gaps (not shown) between the chuck contact surface and the wafer 20. A size of the gap is typically in the range of 5 microns due to variations across the chuck contact surface 60 generally caused by mechanical machining of the chuck surface. Furthermore, the gap width between chuck and wafer surfaces varies due to a waviness of the conventional chuck surface. This gap, is not uniform across wafer, and further varies depending on clamping conditions.
A thickness of the insulating layer 40 between the clamp electrode 30 and the wafer 20 affects a local clamping force, thereby impacting thermal uniformity across the wafer. Conventional manufacturing methods provide poor control over this dimension, however. Non-uniformities in the insulating layer 40 and the physical gap between the clamp 10 and wafer 20 produce potentially large spatial variations in clamping pressure, making precise temperature control difficult. Models and measurements indicate that, conventionally, an average gap width typically varies between 2 microns and 10 microns, depending on the surface and clamping conditions. This relatively large and uncontrollable gap width across the wafer typically results in a lower cooling capability and a non-uniform temperature across the wafer.
Still further, electrical connections to electrodes of the ESCs of the prior art have typically proven to be difficult to form. Conventionally, a wire is soldered beneath the electrodes in a center portion of the electrodes. Such soldering can disadvantageously perturb the heat conduction uniformity across the wafer.
Thus, there is a need in the art for a method of manufacturing an improved electrostatic chuck that provides a uniform HTC which is readily adjustable during processing, as well as a chuck which provides a higher thermal transfer ability in both cooling and heating of the wafer. Furthermore, a need exists for an electrostatic chuck that provides a clamping surface which is operable to significantly limit particulate contamination during wafer processing.